Lattice Semiconductor
PCI Express User’s Guide
TLPs are framed by placing a STP Symbol at the start of the TLP and an END Symbol or EDB Symbol at the end
of the TLP. DLLPs are framed by placing an SDP Symbol at the start of the DLLP and an END Symbol at the end of
the DLLP.
Link Training and Status State Machine (LTSSM)
The LTSSM is a set of interacting state machines implemented as per PCI Express base speci?cation 1.0a section
4.2.5, which includes the following category of state functions:
Detect: To detect whether the far end receiver is powered on or not.
Polling: Transmission and reception of training ordered-sets to establish bit lock and symbol lock.
Con?guration: Transmission and reception with negotiated data rate with con?gured link width.
Recovery: Transmission and reception of training ordered-sets to re-establish bit lock and symbol lock.
L0: Normal operation where data and control packets are transmitted and received.
L0s: Power saving state.
L1: Additional power saving state.
L2: State to conserve power aggressively.
External Loop Back: Loop back between receiver and transmitter for testing and validation purposes.
Disabled: Link is disabled.
Link Control Reset: Link is reset.
Note: The Lattice PCI Express IP core currently does not support L0s, L1, L2 and External Loopback states.
Link Width and Lane Sequence Negotiation (LWLSN)
The link width and lane sequence negotiation logic helps the LTSSM block to negotiate and ?nalize the link and
lane number of the core as part of the training process. The core follows the steps as speci?ed in the PCI Express
spec 1.0a for an end point device.
Data Link Layer Implementation
The Data Link Layer tracks the state of the link. It communicates link status with the Transaction and Physical Lay-
ers, and performs Link Management through the Physical Layer.
Before starting normal operation following power-up or interconnect reset it is necessary to initialize ?ow control for
the virtual channel. The TLP traf?c starts only after this ?ow control initialization. This ?ow control initialization is
implemented in the Data Link layer according to PCI Express Speci?cation 1.0a .
Transmit Path
Transmit TLP Block
The Transmit TLP processing block implements the Data Link Layer requirements for TLPs; sequence number gen-
eration mechanism and LCRC calculation. It appends the information to the TLP that is getting transmitted. Also it
implements the mechanism to resend the same TLP if a retry is requested from the receiver component. To support
this mechanism it has to store the whole TLP that is being transmitted until this component receives an ACK for that
particular TLP or until time-out indication occurs.
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相关PDF资料
PCM18XH2 PROCESSOR MODULE MPLAB-ICE 2000
PCM18XN0 PROCESSOR MODULE FOR ICE2000
PDA-B-24-615-E-2B1-1-C CIRCUIT BREAKER MAG 1P 15A
PFMF.260.2 PFMF PTC FUSE SMT 2.6A 1812
PFNF.200.2 PFNF PTC FUSE SMT 2A 1206
PFRY.375 PTC-FUSE RADIAL 72 VDC
PFSM.150.33.2 FUSE PTC 8A 15V FST-TRIP SMD
PFUF.150.2 FUSE PTC 3A 6V RESET SMD
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